SAFE-SU: A Modular Performance Monitor Unit for Secure Hardware Acceleration
The SMARTY Project has developed SafeSU, a Performance Monitor Unit (PMU) designed to enhance observability and controllability in secure hardware accelerators. SafeSU is AMBA AHB/AXI-compliant and integrates with multicore systems to monitor and manage contention, latency, and resource usage in real time.
Core Functionality
SafeSU consists of three key components:
- Contention-Cycle Stack (CCS): Provides multicore interference breakdown for observability.
- Request Duration Counter (RDC): Measures high-watermark latencies per core, aiding in worst-case execution time estimation.
- Maximum-Contention Control Unit (MCCU): Enforces interference quotas, triggering alerts when predefined thresholds are exceeded.
Interfaces & Programmability
- Monitoring Interface: Snoops traffic via AHB/AXI, ideal for shared memory/cache access points.
- Programming Interface: Uses AMBA APB (future extension to AXI planned) for configuring control registers, including self-test modes and crossbar routing.
- Crossbar: Routes any input event to 24 configurable counters, enabling flexible performance tracking.
Key Features
- Self-test mode: Validates functionality by injecting fixed input patterns.
- Overflow detection: Counters wrap on overflow, with interrupt triggers for threshold breaches.
- MCCU-based quota enforcement: Tracks contention per core, deducting weights from allocated quotas and raising interrupts on exhaustion.
- RDC watermarking: Captures maximum pulse durations for latency-critical events.
Applications
SafeSU is particularly valuable in secure SoC designs, where real-time monitoring of multicore interference ensures deterministic performance and resource fairness. Its modularity makes it adaptable for quantum-resistant accelerators, edge AI, and cyber-physical systems.
For deeper technical insights, refer to the full SMARTY Project deliverables.