1308, 2025

SAFE-SU: A Modular Performance Monitor Unit for Secure Hardware Acceleration 

The SMARTY Project has developed SafeSU, a Performance Monitor Unit (PMU) designed to enhance observability and controllability in secure hardware accelerators. SafeSU is AMBA AHB/AXI-compliant and integrates with multicore systems to monitor and manage contention, latency, and resource usage in real time.  Core Functionality  SafeSU consists of three key components:  Interfaces & Programmability   Key Features  Applications  SafeSU is particularly valuable in secure SoC designs, where real-time monitoring of multicore interference

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1108, 2025

Post-Quantum Cryptography Acceleration for Edge Computing 

As quantum computing continues to evolve, existing public-key cryptographic schemes are becoming increasingly vulnerable. To address this, the SMARTY Project is advancing hardware acceleration for Post-Quantum Cryptography (PQC) within edge computing environments.  Led by BSC, the effort focuses on integrating PQC capabilities into the SELENE SoC, a RISC-V-based platform, using High-Level Synthesis (HLS) to accelerate the development of hardware modules that implement two NIST standardization candidates:  Design Highlights  System Integration 

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